Design
A chip starts as text. Designers write RTL (register-transfer level) code in a hardware language such as Verilog. It says what happens on each clock tick: here, at every rising edge, register q stores a AND b.
A synthesis tool turns the RTL into a netlist: a list of real logic cells and the wires joining them. Every cell comes from a standard-cell library, ready-made gates and flip-flops the factory knows how to build.
Physical design
Physical design begins. The floorplan fixes the size of the die (the chip's rectangle of silicon), puts input and output pads around its edge, and lays power and ground rails across it for the cells to share.
Placement gives every cell a spot. Standard cells all have the same height, so they line up in rows like books on shelves. The tool keeps cells that talk to each other close together, so wires stay short.
The clock must reach every flip-flop at almost the same moment. Clock tree synthesis builds a branching tree of wires and buffers (small amplifiers) with equal paths, so the difference in arrival times, called skew, stays small.
Routing draws the real wires in metal layers stacked above the transistors. One layer runs mostly left to right, the next mostly front to back, joined by vias. The open SkyWater 130 nm process has five metal layers.
Sign-off
Sign-off tests the finished layout. Static timing analysis adds up the delay along every path between flip-flops. At 1 GHz one clock period is 1 ns, so a 0.82 ns path fits, with 0.18 ns to spare: the slack.
Physical verification checks the drawing itself. DRC (design rule check) makes sure every shape obeys the factory's rules, such as minimum width and spacing. LVS (layout versus schematic) confirms the layout is the same circuit as the netlist.
Silicon
When every check passes, the design is taped out: the layout goes to the factory, often as a GDSII file of shapes on every layer. From it the factory makes a set of masks, one per layer pattern, like stencils.
Fabrication builds many dies at once on a silicon wafer. Light shines through or off a mask onto light-sensitive resist; the pattern is then etched or filled, one layer at a time. An Intel processor takes over 2,000 steps and about three months.
Every die is tested on the wafer with fine probes, then the wafer is cut apart. Good dies are sealed in packages that protect them and connect them to pins. A final test checks each packaged chip before it ships.
A process node name such as 5 nm is a label, not a size: on 5 nm chips the gate pitch is about 48 nm and the metal pitch 36 nm. Masks alone cost millions: about $2 million for one 45 nm set in 2008.
Inside the step
;; step 1/12 · rtl ;; about: RTL code RTL = register-transfer level always @(posedge clk) q <= a & b; @(posedge clk) on each rising clock edge q <= a & b q stores a AND b the same idea in Python: q = a & b # once per clock tick
The steps follow the standard ASIC flow described in Weste and Harris, CMOS VLSI Design (4th ed.), and used by the open OpenROAD tools: synthesis, floorplan, placement, clock tree synthesis, routing, sign-off, then tape-out. The delays in the timing step are example numbers chosen to show the sum, not values from a real cell library. At 1 GHz one clock period is 1/1,000,000,000 s = 1 ns.