Lesson 20 · Memory elements and clocks

Clocks and timing

A crystal oscillator makes a steady square wave, the clock, and every flip-flop updates on its rising edge. Learn how frequency and period are linked (3 GHz means a period of about 0.33 ns), then watch a new value race through three gates from one flip-flop to the next and see why the slowest path between flip-flops sets the highest clock speed, and how clock skew eats into it.

11 min11 steps5 questionsIntermediate

Fig 20 · Interactive

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5 quick questions

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01When does a flip-flop copy its D input to its Q output?

A flip-flop updates on the clock's rising edge, the jump from 0 to 1, and holds its output still in between.

02A clock runs at 2 GHz. How long is one period?

Period = 1 ÷ frequency = 1 ÷ (2 × 10⁹) s = 0.5 × 10⁻⁹ s = 0.5 ns, which is 500 picoseconds.

03Clock-to-Q is 100 ps, the gates take 300 ps and setup time is 50 ps. What is the shortest period this path allows?

The value needs 100 + 300 = 400 ps to reach D, and must then be steady for 50 ps before the edge: 450 ps in total.

04What happens if the clock is too fast for the critical path?

Gate delays do not shrink with the clock. If the period is shorter than the path needs, the receiving flip-flop captures the value too early and the result is wrong.

05What is clock skew?

Clock wires of different lengths deliver the same edge at slightly different times. In the worst case that difference is added to the time a path needs.

Key terms

Glossary

Clock: A signal that flips between 0 and 1 at a steady rate; every flip-flop in a synchronous circuit updates in step with it.
Crystal oscillator: A circuit built around a small slice of quartz that vibrates at a very stable rate, used as the source of a clock.
Rising edge: The moment the clock jumps from 0 to 1. Flip-flops copy their input on this edge.
Frequency and period: Frequency is how many clock cycles happen per second (hertz); the period is the time of one cycle. Period = 1 ÷ frequency.
Propagation delay: The time a gate or circuit takes for its output to change after its input changes.
Setup time: How long before a clock edge a flip-flop's input must already be steady for it to be stored reliably.
Critical path: The slowest path from one flip-flop to the next; it sets the shortest possible clock period and so the highest clock speed.
Clock skew: The difference in arrival time of the same clock edge at different flip-flops.

Fine print

Notes and sources

A quartz crystal resonates at a very stable frequency, and an oscillator circuit built around it gives a steady clock (Horowitz and Hill, The Art of Electronics, 3rd ed., chapter 7). Processors use a phase-locked loop to multiply a slower crystal reference up to their GHz core clock.
Period and frequency are each other's inverse: T = 1 / f. 3 GHz is 3 × 10⁹ cycles per second, so T = 1 / (3 × 10⁹) s ≈ 3.33 × 10⁻¹⁰ s ≈ 0.33 ns (NIST SI prefixes: giga 10⁹, nano 10⁻⁹, pico 10⁻¹²).
The setup-time rule for a path between two flip-flops is Tc ≥ tpcq + tpd + tsetup: clock-to-Q delay, plus the propagation delay of the logic, plus the setup time. The slowest such path is the critical path and sets the shortest period, so the highest clock frequency (Harris and Harris, Digital Design and Computer Architecture, section 3.5).
Clock skew is the difference in arrival time of the clock edge at different flip-flops. In the worst case it is added to the path: Tc ≥ tpcq + tpd + tsetup + tskew (Harris and Harris, section 3.5.3). Skew can also cause hold-time errors, which this lesson leaves out.
The delays in the race (100 ps clock-to-Q, 100 ps per gate stage, 50 ps setup) are round example numbers so the sums stay easy. Real gates list their delays in their datasheets; older chips such as the 74HC00 take nanoseconds, gates inside a modern processor only picoseconds.
In Python, 1e-12 is 10⁻¹² (one picosecond in seconds) and 3e9 is 3 × 10⁹, so 1 / 3e9 gives the period of a 3 GHz clock in seconds.

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