The clock
A tiny slice of quartz crystal vibrates at a very steady rate when powered. An oscillator circuit turns that vibration into a clock signal: a wire that flips between 0 and 1, again and again, at a fixed pace.
Drawn against time, the clock looks like a row of square teeth, so it is called a square wave. The moment it jumps from 0 up to 1 is called a rising edge.
The same clock wire runs to every flip-flop. A flip-flop is a 1-bit memory. On each rising edge, and only then, it copies its D input to its Q output. So the whole circuit steps forward in time with the beat.
Frequency counts clock cycles per second. The period is the time of one cycle: period = 1 ÷ frequency. A 3 GHz clock ticks three billion times a second, so one period lasts about 0.33 ns (nanoseconds, billionths of a second).
The race
Now a 2 GHz clock. On a rising edge, flip-flop 1 copies its input, a 1, to its output. Even that takes a moment, the clock-to-Q delay: 100 picoseconds (trillionths of a second) in this example.
A gate's output does not change the instant its input does. That wait is its propagation delay. Here each gate with its wire takes 100 ps, so three gates in a row take 300 ps.
Flip-flop 2 copies D on the next rising edge. But D must be steady a little before that edge, the setup time: 50 ps here. A value that arrives inside that window may be missed.
At 2 GHz one period is 500 ps. The path needs 100 + 300 + 50 = 450 ps. The value arrives with 50 ps to spare, and flip-flop 2 stores the 1 on the next edge.
At 3 GHz the period shrinks to about 333 ps, but the path still needs 450. The next edge comes before the value arrives, so flip-flop 2 keeps its old 0. The circuit now gives a wrong answer.
Top speed
A real chip has millions of paths between flip-flops. The slowest one is the critical path, and the period can be no shorter. Here that is 450 ps, so the top speed is 1 ÷ 450 ps ≈ 2.22 GHz.
The clock wire to flip-flop 1 is longer, so its edge arrives 60 ps late. That difference is clock skew. The value leaves late and misses the 2 GHz edge. Designers balance clock wires to keep skew small.
The timing budget
;; step 1/11 · crystal ;; about: Crystal, Clock crystal oscillator quartz vibrates at a fixed rate → a steady 0, 1, 0, 1 … signal In a processor, a circuit called a phase-locked loop (PLL) multiplies the crystal's slower beat up to the GHz core clock.
The delays in the race (100 ps clock-to-Q, 100 ps per gate stage, 50 ps setup) are round example numbers so the sums stay easy. Real gates list their delays in their datasheets; older chips such as the 74HC00 take nanoseconds, gates inside a modern processor only picoseconds. In Python, 1e-12 is 10⁻¹² (one picosecond in seconds) and 3e9 is 3 × 10⁹, so 1 / 3e9 gives the period of a 3 GHz clock in seconds.