The CMOS inverter
Put a p-channel MOSFET on the supply rail and an n-channel MOSFET on the ground rail, join their gates and their drains, and you have the simplest logic gate. Watch input 1 turn the NMOS on and pull the output to 0, and input 0 do the opposite: a NOT gate. Then see why CMOS draws almost no current at rest, and the short burst it takes while it switches.
5 quick questions
Pick an answer to see why. Your score saves with your progress.
01In a CMOS inverter, which transistor connects the output to the supply rail?
The p-channel MOSFET (PMOS) sits between the supply rail and the output; the n-channel MOSFET (NMOS) sits between the output and ground.
02The input is 1 (1.0 V). What happens?
1.0 V is above the NMOS threshold (0.43 V), so the NMOS conducts. The PMOS gate is level with its source, so it is off. The output is joined to ground only: 0.
03Which logic gate is a CMOS inverter?
It outputs the opposite of its input: 0 gives 1 and 1 gives 0. That is NOT, which is why it is also called an inverter.
04Why does a CMOS inverter use almost no power when its input is not changing?
With input 1 the PMOS is off; with input 0 the NMOS is off. Either way the path from supply to ground is broken, so only a tiny leakage current flows.
05When does a CMOS inverter take a burst of current from the supply?
While the input passes between the two thresholds (0.43 V and 0.6 V in this model) both transistors conduct a little, and charging the output also takes current. So CMOS power is used mainly when it switches.
Glossary
- CMOS
- Complementary metal-oxide-semiconductor: circuits built from pairs of p-channel and n-channel MOSFETs, so one is off whenever the other is on.
- Inverter
- A NOT gate: its output is the opposite of its input. In CMOS it takes one PMOS and one NMOS.
- Supply rail (VDD)
- A wire held at the circuit's supply voltage, standing for logic 1. In this lesson it is +1.0 V.
- Ground rail (GND)
- A wire held at 0 V, standing for logic 0, where currents return.
- Pull-up / pull-down
- The transistor that joins the output to the supply (pull-up, the PMOS) or to ground (pull-down, the NMOS).
- Threshold voltage (Vth)
- The gate-to-source voltage at which a MOSFET starts to turn on: 0.43 V for the NMOS and -0.4 V for the PMOS in the cited textbook process.
- Leakage current
- The tiny current a transistor still lets through when it is off.
- Static and dynamic power
- Static power is used while nothing changes (tiny in CMOS, just leakage); dynamic power is used each time the gate switches.
Notes and sources
- The board is a teaching model: the +1.0 V supply matches the gate "high" of the transistors lesson and is not taken from one datasheet. Real chips use their own supply voltage.
- Threshold values: NMOS 0.43 V and PMOS -0.4 V for the generic 0.25 µm CMOS process in MIT 6.374 (after Rabaey, Chandrakasan and Nikolić, Digital Integrated Circuits). With them, both transistors conduct only while the input is between 0.43 V and 0.6 V.
- An off transistor is not perfectly off: a small leakage current still flows. The figure shows it as a sliver on the current meter.
- Most of the power a CMOS gate uses goes into charging and emptying the wires and gates its output drives; the brief overlap current while switching adds a smaller share.
- CMOS was shown in 1963 by Frank Wanlass and C. T. Sah of the Fairchild R&D laboratory; Wanlass patented it (Computer History Museum).
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