The parts
The back rail is the supply, held at 1.0 V: that stands for 1. The front rail is ground, 0 V: that stands for 0. The circuit's job is to join its output to one rail or the other.
Between the rails stand two transistors, one above the other. The p-channel one (PMOS) connects to the supply; the n-channel one (NMOS) connects to ground. Their drains meet in the middle: that point is the output.
The input wire splits and feeds the gate of both transistors, so they always see the same voltage. The trick is that the two kinds react to it in opposite ways.
Switching
Set the input to 1 (1.0 V). That is above the NMOS threshold, so the NMOS switches on. The PMOS gate is now level with its source, so the PMOS switches off.
Only the NMOS conducts, so the output is joined to ground and cut off from the supply. Any charge on it drains away and it settles at 0 V. Input 1 gives output 0.
Now set the input to 0. The NMOS switches off. The PMOS gate is now 1.0 V below its source, past its threshold, so the PMOS switches on.
Only the PMOS conducts, so the output is joined to the supply and cut off from ground. A little current flows in until it reaches 1.0 V, then stops. Input 0 gives output 1.
NOT gate
Whatever goes in, the opposite comes out: 1 gives 0 and 0 gives 1. That is a NOT gate, also called an inverter. Logic diagrams draw it as a triangle with a small circle.
Power
In either steady state one transistor is off, so there is never a path straight from supply to ground. Only a tiny leakage current flows. That is why CMOS chips use so little power when idle.
As the input crosses between 0.43 V and 0.6 V, both transistors are partly on and a short burst flows straight to ground. Filling and emptying the output takes current too. So CMOS uses power mainly when it switches.
Bigger picture
CMOS means complementary metal-oxide-semiconductor: an opposite pair, so one is off whenever the other is on. Frank Wanlass and C. T. Sah showed it in 1963. More pairs build NAND, NOR and the other gates.
In detail
;; step 1/11 · rails Supply rail (V_DD) = +1.0 V -> logic 1 Ground rail (GND) = 0 V -> logic 0 A rail is a wire held at a fixed voltage that many parts connect to. (1.0 V is this lesson's teaching value; real chips use their own supply.)
The board is a teaching model: the +1.0 V supply matches the gate "high" of the transistors lesson and is not taken from one datasheet. Real chips use their own supply voltage. Threshold values: NMOS 0.43 V and PMOS -0.4 V for the generic 0.25 µm CMOS process in MIT 6.374 (after Rabaey, Chandrakasan and Nikolić, Digital Integrated Circuits). With them, both transistors conduct only while the input is between 0.43 V and 0.6 V. An off transistor is not perfectly off: a small leakage current still flows. The figure shows it as a sliver on the current meter. Most of the power a CMOS gate uses goes into charging and emptying the wires and gates its output drives; the brief overlap current while switching adds a smaller share.