Decoding
The datapath has registers, an ALU, memory and multiplexers (muxes), but on its own it does nothing. Every clock cycle something must tell each part what to do. That is the control unit's job: it reads each instruction and sets the parts up.
A TINY-8 instruction is 2 bytes. Byte 1 holds the opcode (4 bits) and two register numbers. Byte 2 is the immediate: a number written right in the instruction. The opcode says which of 16 instructions it is. Here: 0001, LDI r3, 1.
Out come control signals, one wire per job. RegWrite lets a register change. ALUSrc and MemToReg set two muxes. ALUOp picks the ALU's operation. MemRead and MemWrite drive memory. PCSrc picks the next PC: PC + 2 or a jump.
The signals depend only on the opcode, so they fit in a table with 16 rows, one per instruction. Watch the opcode count from 0000 to 1111: each row sets the lamps. Only JZ and JNZ also look at the Z flag.
Four instructions
LDI r3, 1 puts 1 in r3. Opcode 0001 sets RegWrite 1, ALUSrc 1 so the ALU gets the immediate byte, ALUOp PASS and MemToReg 0. The 1 flows through the ALU into r3, and the PC moves on to 4.
Opcode 0110 sets RegWrite 1, ALUSrc 0 so both ALU inputs come from registers, and ALUOp SUB. r2 = 3 − 1 = 2 is written back. The ALU also sets the Z flag to 0, because 2 is not zero.
Opcode 0011 sets MemWrite 1 and RegWrite 0: this time no register may change. r2's value, 2, is written to memory at address 32, the immediate byte. The ALU is not needed, so ALUOp does not matter.
Opcode 1101 jumps only if the Z flag is 0. Z is 0, since the last result, 2, was not zero, so PCSrc becomes 1: the PC mux picks the jump target 4, not PC + 2 = 10. The loop runs again.
Building it
One way: logic gates. A decoder turns the 4 opcode bits into 16 lines, one per instruction; OR gates join the lines each signal needs. PCSrc = JMP OR (JZ AND Z) OR (JNZ AND NOT Z). Fast, but fixed once built.
The other way: keep the table in a small memory, the control store. The opcode and the Z flag together form the address; the word read out is the signals. So JNZ has two words: Z 0 gives PCSrc 1, Z 1 gives PCSrc 0.
Opcode in, signals out
;; step 1/10 · the-boss datapath = the parts that hold and change data registers r0-r3 · ALU · memory · muxes control unit = tells those parts what to do input: the opcode (+ the Z flag) output: control signals, one wire per job TINY-8: 8-bit data, 4 registers, 16 instructions, each 2 bytes.
A dash in the table means don't care: the signal has no effect for that instruction, so the designer may let the circuit output either value. The figure shows those as 0. Every encoding, register value and PC in the figure comes from TINY-8, the course's teaching CPU, and its reference simulator. The figure draws seven of the control signals; the full table also has FlagWrite, OutWrite (for OUT), Halt and the input port as a third write-back choice (for IN).