ADDR 0LDAADDR 1ADDADDR 2STAADDR 3JMP 0+1ADD 101842101010101DECIMAL601T 801T 401T 201T 1010110PC
Lit wire with moving dashes: a signal is flowingLamps: a glowing lamp is a 1, a dark one a 0 (weights 8 4 2 1)Token on the loop: the next value travelling from the adder back to the registerPC flag: the instruction the program counter points atA synchronous counter is a register plus an adder that adds 1: on every rising clock edge the register saves the adder's answer, so the count goes up by one and wraps from 15 to 0. A ripple counter chains toggle flip-flops instead; each bit runs at half the frequency of the one before, and a change ripples through the stages one at a time. Real parts: Texas Instruments' SN74HC161 is a 4-bit synchronous binary counter whose clear input works without the clock; the SN74HC393 holds two 4-bit ripple counters built from toggle flip-flops, each clocked by the one before. Nearly all quartz watches use a 32,768 Hz crystal; 32,768 is 2^15, so a 15-stage binary counter overflows once per second.

Register plus adder

  1. A counter starts with a register: four flip-flops that each remember one bit. The lamps show the bits with weights 8, 4, 2 and 1. Here 0110 means 4 + 2, so the readout says 6.

Counting, wrapping, reset

Ripple counters

What counters do

Bit by bit

;; step 1/11 · register-holds
;; about: Register, Decimal
bits   8 4 2 1
       0 1 1 0

0×8 + 1×4 + 1×2 + 0×1 = 6

Four bits can hold 2^4 = 16 numbers:
0000 (0) up to 1111 (15).

A rising clock edge is the instant the clock signal goes from low (0) to high (1). Flip-flops in a register copy their input only at that instant (Harris and Harris, Digital Design and Computer Architecture, sections 3.2 and 5.4.1). The figure slows the ripple down so you can see it. In a 74HC393 each stage adds a delay of roughly 13 nanoseconds (typical), so a 4-bit ripple is wrong for only a few tens of nanoseconds.