CLKDsetupholdD FLIP-FLOP01DQE01D LATCH0101DQE01LEADERDQE01FOLLOWER011
Lit wire with moving dashes: it carries a 1Latch top: glowing channel = open (transparent), gap = closed; the lens shows the stored bitTiming card: the clock and D over time; arrows mark rising edges, the cursor marks nowDashed outline: the two latches and the NOT gate that make one flip-flopA gated D latch is transparent (Q follows D) while its enable is 1 and holds Q while it is 0. Because it reacts for the whole time enable is 1, it is called level-sensitive (Harris and Harris, Digital Design and Computer Architecture, section 3.2). An edge-triggered D flip-flop is two D latches in a row on opposite clocks. Textbooks call them master and slave; here they are the leader and the follower. Q copies D only at the rising edge of the clock and holds it for the rest of the cycle. Texas Instruments' SN74LVC74A holds two positive-edge-triggered D flip-flops. At 3.3 V its datasheet requires D to be steady at least 3 ns before the clock's rising edge (setup time) and 1 ns after it (hold time), with a clock of up to 100 MHz.

The gated D latch

  1. A gated D latch stores one bit. It has a data input D, an enable input E and an output Q, the bit it remembers. D stands for data. One wire carries the bit, so set and reset can never clash.

The edge-triggered flip-flop

Timing rules

Moment by moment

;; step 1/10 · d-latch
;; about: D input, Enable / clock, D latch, Latch Q
inputs:  D (data), E (enable)
output:  Q (the stored bit)

E = 1  →  Q = D
E = 0  →  Q keeps its value

Here the enable comes from the clock lamp.

In the figure each column of the timing card is one moment. Real clocks tick far faster; the frames are slowed down so you can watch them.