One cell
A DRAM cell stores a bit as charge in a capacitor, a tiny store of charge: full is 1, empty is 0. The word line (a switch wire) opens its transistor, the door; the bit line (a data wire) fills or empties the capacitor.
SRAM, the other kind of memory chip, holds each bit in a loop of six transistors. DRAM needs only one transistor and one capacitor, so many more bits fit on a chip and each bit costs less.
The array
Cells sit in a grid. All cells in a row share one word line; all cells in a column share one bit line. The row decoder turns a row address into the one word line it should raise.
A capacitor is not sealed. Its charge slowly leaks away, so a 1 drains toward 0. Once it falls below half, the chip can no longer tell it from a 0. This is why it is called dynamic RAM.
Reading a row
To read, the decoder raises one word line and every door in that row opens. Each cell shares its tiny charge with its long bit line, which only nudges the bit line's voltage a little up or down.
A sense amplifier sits at the end of every bit line. It spots the small nudge and pushes it all the way to a clear 0 or 1. Together they now hold the whole row, called the row buffer.
Sharing its charge left each cell half empty, so reading destroys the bit. The sense amplifiers drive full values back up the bit lines and refill the row before the word line closes.
A column address picks which bit of the row buffer goes out to the chip's data pins. While the row stays open, reading another column is quick: no new word line is needed.
Keeping it alive
To beat the leak, the chip keeps reading and rewriting every row in turn. This is refresh. The standard gives each row at most 64 ms, so a DDR4 chip gets a refresh command about every 7.8 µs.
A chip splits its cells into banks: separate grids, each with its own rows and sense amplifiers. While one bank has a row open, another bank can open its own row. A DDR4 chip has 8 or 16 banks.
Gigabytes of memory have to be small and cheap, so a computer's main memory is DRAM. Faster SRAM needs no refresh but takes more room per bit, so it is kept for the small caches inside the processor.
Inside the step
;; step 1/11 · one-cell ;; about: One DRAM cell 1T1C: one transistor + one capacitor word line on → door open bit line high → capacitor fills (1) bit line low → capacitor empties (0) word line off → door shut, the bit stays Robert Dennard, IBM: patent 1968
The figure runs enormously slowed down. Real DRAM cells keep their charge for tens of milliseconds or longer, and the standard refreshes each row at least every 64 ms. A cell holds far less charge than its long bit line, so sharing moves the bit line only slightly. That is why a sense amplifier is needed, and why the cell is left near half full until it is written back (Harris and Harris, section 5.5; Drepper, section 2.1).