The fabric
An FPGA, short for field-programmable gate array, is a chip full of blank building blocks: logic tiles, wires with switches between them, and blocks of memory and maths. You decide what it does after it is made.
Lookup tables
Each tile holds a lookup table, or LUT. A 4-input LUT is 16 one-bit memory cells, one for each pattern of its four inputs. The inputs pick one cell, and that cell's bit becomes the output.
To make a 4-input AND, store a 1 in the last cell only, the one that 1 1 1 1 picks. Every other pattern picks a 0. No AND gate is built: the stored table is the logic.
Load 16 different bits and the very same LUT becomes XOR: its output is 1 when an odd number of inputs are 1. Sixteen bits can be set 2¹⁶ = 65,536 ways, so one 4-input LUT can act as 65,536 different functions.
Memory and wiring
Beside the LUT sits a flip-flop. When the clock ticks from 0 to 1, it copies the LUT's output into its stored output, called Q, and holds it until the next tick, even if the inputs change. That gives the circuit memory.
Tiles are joined by routing: tracks of wire with a switch where they cross. Each switch is set by one configuration bit. Closed switches link one tile's output to another tile's input, so a path lights across the chip.
Some jobs would need too many LUTs, so FPGAs add fixed blocks in columns. Block RAM stores data: one AMD 7 series block holds 36 Kb. DSP (digital signal processing) slices do fast maths: each has a 25 by 18 bit multiplier.
Configuring it
A design tool turns your hardware description, such as Verilog, into a bitstream: a file holding every LUT bit and switch bit. At power-up it is loaded into the chip's configuration memory, and the fabric becomes your circuit.
Most FPGAs keep their configuration in SRAM, which forgets when power goes off, so it reloads at every start. Load a new bitstream and you get a new circuit. That suits prototypes, small-batch products and custom accelerators.
Inside the step
;; step 1/9 · fabric ;; about: Logic tiles, Routing switches, Block RAM, DSP slices FPGA = field-programmable gate array logic tiles LUT + flip-flop, in a grid routing wire tracks + switches block RAM memory columns DSP slices multiplier columns "field-programmable": set up by you, after the chip leaves the factory.
A k-input LUT is 2 to the power k one-bit memory cells plus a selector: the inputs choose which cell's bit reaches the output. The 4-input LUT here is the one in each logic element of an Intel Cyclone IV (Harris and Harris, Digital Design and Computer Architecture, section 5.6.2). In Python a list can stand in for the LUT: lut[i] reads cell i, and a << 3 | b << 2 | c << 1 | d turns four 0/1 inputs into a cell number from 0 to 15.