Lesson 39 · Digital design practice

Describing hardware: Verilog

Real chips hold far too many gates to draw by hand, so engineers describe them in text, in a hardware description language. In Verilog, a module lists its input and output ports; assign lines become gates that work all the time; an always @(posedge clk) block becomes flip-flops that change only at a clock edge. Watch each line light up with the circuit it describes, then see a synthesis tool turn the text into gates.

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01What does a hardware description language such as Verilog describe?

An HDL describes hardware: modules, their ports, the logic between them and the flip-flops that store values. A synthesis tool turns that description into gates.

02A module contains assign s = a ^ b ^ cin; What happens when input b changes?

assign is a continuous assignment: it becomes XOR gates wired to s, so s follows its inputs at all times. Only blocks clocked with always @(posedge clk) wait for an edge.

03Two assign lines in the same module are swapped. What changes in the circuit?

Each assign is its own piece of circuit, and all of them work at the same moment. Their order in the file does not matter, unlike lines in a Python program.

04In always @(posedge clk) count <= count + 1; with count declared reg [3:0], count is 15. What is it after the next rising edge?

Four bits hold 16 values, 0 to 15. 15 + 1 needs a fifth bit, which is dropped, so the count wraps to 0.

05What does a synthesis tool such as Yosys produce from Verilog?

Synthesis reads the HDL and writes a netlist of gates and flip-flops. That netlist then configures an FPGA or is laid out as a real chip.

Key terms

Glossary

Hardware description language (HDL): A language for describing circuits as text, such as Verilog (IEEE 1364, now part of SystemVerilog, IEEE 1800) or VHDL (IEEE 1076).
Module: Verilog's building block: a named box with ports; bigger designs plug modules together.
Port: A named wire crossing a module's edge, declared as input or output.
assign: A continuous assignment: the wire on the left always equals the expression on the right. It describes combinational logic.
always @(posedge clk): A block that runs at every rising edge of clk, the moment the clock goes from 0 to 1. Values saved in it become flip-flops.
Nonblocking assignment (<=): The assignment used in clocked blocks: every right-hand side is read first, then all the flip-flops update together.
Synthesis: Turning HDL text into a netlist of gates and flip-flops.
Netlist: A list of a circuit's parts and the wires that connect them.

Fine print

Notes and sources

Verilog was standardised as IEEE 1364 (last edition 1364-2005). Since 2009 it is part of SystemVerilog, IEEE 1800, which adds features for testing designs. The other widely used HDL is VHDL, IEEE 1076.
assign is a continuous assignment: its left side is driven by the expression all the time, like a wire soldered to a gate's output. Because every assign is working at once, their order in the file does not matter (Harris and Harris, chapter 4).
In Verilog, & binds tighter than ^, and ^ tighter than |, so a&b | cin&(a^b) would mean the same thing. The card writes the brackets anyway to make the gates easy to see.
Inside always @(posedge clk), write <= (nonblocking). Every right-hand side is read first, with the values from just before the edge, and all the flip-flops update together. Mixing up = and <= is a classic bug (Cummings, SNUG 2000).
A reg declared without a starting value is x (unknown) in simulation, and x + 1 is still x, so a counter without a reset never leaves x. Many FPGAs do power up with their flip-flops at 0, but designs use an explicit reset so simulation and hardware agree.
Synthesis reads the HDL and writes a netlist: a list of gates and flip-flops and the wires between them. Yosys is an open-source synthesis tool; FPGA and chip vendors ship their own. The netlist then goes on to place and route.

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