Test before you build
Making a chip takes months, and a wrong transistor cannot be patched later. So designers first simulate: a program, the simulator, runs the HDL (hardware description language) design on an ordinary computer and works out every signal, step by step.
The testbench
The design being tested is the DUT, short for design under test: here a full adder. The testbench is extra code around it. It feeds the inputs and watches the outputs, and it is never built into the chip.
A real chip gets its clock from outside. In simulation the testbench makes one: high for 5 ns, low for 5 ns, so one tick every 10 ns. Each rising edge applies a test; each falling edge checks it.
A test vector is one line: the inputs to try and the outputs they should give. The expected answers come from a reference model, a simple trusted program that computes the same thing.
On each rising edge the testbench takes the next vector and drives its bits onto the design's inputs a, b and cin. The adder then works out its outputs, s and cout.
On the falling edge the checker compares the design's outputs with the expected ones. That comparison is an assertion: a line that must be true, and reports an error when it is not.
Waveforms and bugs
The simulator records every signal. A waveform viewer draws each one as a line against time: up for 1, down for 0. You read across to see what changed, and when.
Vector 0 1 1 fails: cout should be 1 but the design gives 0. The waveform marks the spot. The code wrote cout = a & b and forgot the carry-in. Fix it and run again.
How much to test
Three inputs give 2 × 2 × 2 = 8 cases, so we can try them all: an exhaustive test. The coverage boxes count which cases were tried. All 8 pass, in 80 ns of simulated time.
A 32-bit adder has 64 input bits: about 585 years of tests at a billion a second. So big blocks get random tests, then directed tests aimed at the gaps. Here six random picks miss four cases.
In simulation a bug costs an edit. In silicon it can cost a recall: a division bug in Intel's Pentium (1994) led to a 475 million dollar charge. That is why teams test so hard before they build.
What the simulator does
;; step 1/11 · why-simulate
;; about: Design under test
HDL design (Verilog)
│ simulator
▼
every signal, worked out in software
found a bug? edit the code, run again
(minutes, not months)
The clock, the vector file and the rising-edge apply / falling-edge check pattern follow the self-checking testbench in Harris and Harris, Digital Design and Computer Architecture (2nd ed.), section 4.9. In Python, ^ and & on the numbers 0 and 1 are XOR and AND, and assert raises an AssertionError when its condition is false. The cocotb library lets you write testbenches like this in Python for real Verilog simulators.