Lesson 31 · Build a processor

A complete CPU: fetch, decode, execute

Put the parts together and run a real program. TINY-8, the course's teaching CPU, fetches each instruction from memory, decodes it in the control unit, executes it in the ALU, writes the result back and moves its program counter on, all in one clock cycle. Watch it add 2 + 3, show 5 on its output port, count r2 down to zero with the Z flag and JNZ, and halt after 13 cycles. Then see why the clock has to wait for the slowest instruction.

12 min12 steps5 questionsBeginner

Fig 31 · Interactive

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5 quick questions

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01LDI r0, 2 must put the number 2 (the instruction's second byte, the immediate) into the ALU. Which control signal makes the ALU's second input the immediate instead of a register?

ALUSrc sets the mux on the ALU's B input: 0 picks a register, 1 picks the immediate. LDI also sets ALUOp to PASS, so the 2 comes out of the ALU unchanged, and RegWrite = 1 lets r0 take it at the clock edge.

02TINY-8 fetches the bytes 51 00 (hex). The first byte is 0101 0001. Which instruction is it?

The top 4 bits 0101 are opcode 5, ADD; the next two bits 00 are the destination r0; the last two bits 01 are the source r1.

03The countdown has just run SUB r2, r3 and r2 became 0. What does JNZ 12 do next?

JNZ means jump if not zero. The SUB result was zero, so the ALU set Z to 1, and the control unit sets PCSrc to 0: PC takes PC + 2 and reaches HALT.

04When do PC, the registers and the flags actually change in a single-cycle CPU?

They are all clocked state. During the cycle the new values travel through the logic; at the rising edge they are all stored at once.

05With the textbook delays, ADD needs 700 ps and JNZ only 325 ps. How long is each clock cycle?

Every instruction gets the same single cycle, so the period must fit the slowest path: 700 ps, about 1.43 GHz at most. Quick instructions like JNZ then sit idle for the rest of the cycle.

Key terms

Glossary

Program counter (PC): A register holding the memory address of the next instruction. It normally steps on by the instruction's size; a jump writes a new address into it.
Fetch and decode: Fetch reads the instruction at PC from memory; decode splits it into opcode, registers and immediate, and the control unit turns the opcode into control signals.
Control signal: A wire from the control unit that steers the datapath, such as RegWrite (a register may change), ALUSrc (the ALU's second input), ALUOp (what the ALU does) or PCSrc (take the jump).
Multiplexer (mux): A switch that passes one of its inputs to its output, chosen by a control signal. The ALUSrc mux picks a register or the immediate; the write-back mux picks what is written to the register.
Execute and write back: The ALU produces the result (for LDI it passes the value through unchanged), and the result is stored in the destination register at the clock edge.
Z flag: A one-bit register the ALU sets to 1 when its result is zero; conditional jumps such as JNZ read it.
Single-cycle CPU: A processor that runs every instruction in exactly one clock cycle, so the cycle must be as long as the slowest instruction.
Critical path: The slowest path through the logic between two clock edges; it sets the shortest possible clock period.

Fine print

Notes and sources

TINY-8 is the course's teaching CPU: 8-bit data, four registers r0 to r3, an 8-bit PC, 256 bytes of shared memory and 2-byte instructions (byte 0 = 4-bit opcode, 2-bit destination, 2-bit source; byte 1 = an immediate or address). Every value in the figure comes from its reference simulator.
In a single-cycle CPU the instruction is simply the memory's output: PC does not change until the edge at the end of the cycle, so those wires hold the instruction steady all cycle long. We label them IR (Harris and Harris, section 7.3).
PC, the registers, the flags and the output port are all clocked state: they change only at the rising clock edge that ends the cycle. Everything between edges is combinational logic settling.
Delays are the textbook example values for a 65 nm process in Harris and Harris, Digital Design and Computer Architecture (2nd ed.), Table 7.6: clock-to-Q 30 ps, memory read 250 ps, register file read 150 ps, multiplexer 25 ps, ALU 200 ps, register file setup 20 ps. As in their analysis, the control unit's delay is assumed to be off the critical path. The rule period ≥ clock-to-Q + logic + setup is the one from the Clocks and timing lesson.
Every instruction waits the full 700 ps, so this run of 13 cycles takes 9100 ps; if each instruction took only its own path it would need 6725 ps. Pipelining, later in this module, wins that time back another way.
The control signals are the TINY-8 control unit's truth table (one row per opcode). LDI is RegWrite 1, ALUSrc 1, ALUOp PASS, MemToReg 0: its immediate goes through the ALU unchanged, so it shares the ALU's path (550 ps) instead of skipping it.
The example program does not use LD, ST or IN, so MemRead and MemWrite stay 0, and the data-memory port and the input port are not drawn; they would add paths but not a slower one than ADD (LD: 575 ps).

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