The parts
A program is just numbers in memory. TINY-8's example is 9 instructions of 2 bytes each, 18 bytes in all. The program counter, PC, holds the address of the next instruction. It starts at 0.
One cycle, phase by phase
Every clock cycle starts with fetch. PC sends address 0 to memory, and memory hands back the two bytes stored there, 10 02 in hexadecimal. They appear on the instruction wires we label IR.
The control unit reads the first byte, 0001 0000: opcode 1, LDI, and the next 2 bits pick r0. From its table it sets RegWrite 1, ALUSrc 1 (use the immediate) and ALUOp PASS. The second byte, 2, is the value.
The ALUSrc mux, a switch that picks one input, sends 2 into the ALU. ALUOp is PASS, so 2 comes out unchanged, and the write-back mux sends it to r0. At the rising edge, r0 takes 2 and PC takes 0 + 2 = 2.
Running the program
That was one clock cycle: fetch, decode, execute, write back and a new PC, all between two rising edges. Now the next cycle at full speed: LDI r1, 3 puts 3 in r1, and PC becomes 4.
ADD r0, r1 gives the ALU, the arithmetic logic unit, real work. The registers send 2 and 3, the ALU adds them, and at the edge r0 becomes 5. The result is not zero, so the Z flag stays 0.
OUT r0 copies r0 to the output port, the CPU's window to the outside world. The control unit sets OutWrite 1; the ALU is not used. At the edge the port shows 5: the program has printed its answer, 2 + 3.
The loop
Next, a countdown. LDI r2, 3 and LDI r3, 1 set a counter and a step, one cycle each. Then SUB r2, r3 makes the ALU compute 3 − 1 = 2, and Z stays 0 because 2 is not zero.
JNZ 12 means jump if not zero. The control unit checks the Z flag: it is 0, so it sets PCSrc to 1, and PC takes the jump target 12 instead of 14 + 2 = 16. The loop runs again.
Round the loop: SUB makes r2 1 and JNZ jumps back. SUB makes r2 0; the result is zero, so Z becomes 1. This time JNZ does not jump, and PC moves on to 16.
At address 16 sits HALT. The control unit sets Halt and the clock stops. The run took 13 clock cycles for 9 instructions, because SUB and JNZ ran three times each. The output port still shows 5.
Cycle time
Each instruction gets one equal cycle, so the clock waits for the slowest. With textbook delays, ADD and SUB need 700 picoseconds (ps) through memory, registers and ALU; JNZ needs only 325 ps. So this CPU ticks at most about 1.43 GHz.
Inside the cycle
;; step 1/12 · program ;; about: Memory, Program counter addr bytes instruction 0 10 02 LDI r0, 2 2 14 03 LDI r1, 3 4 51 00 ADD r0, r1 6 E0 00 OUT r0 8 18 03 LDI r2, 3 10 1C 01 LDI r3, 1 12 6B 00 SUB r2, r3 14 D0 0C JNZ 12 16 00 00 HALT loop: is address 12 (the JNZ jumps there)
PC, the registers, the flags and the output port are all clocked state: they change only at the rising clock edge that ends the cycle. Everything between edges is combinational logic settling. Delays are the textbook example values for a 65 nm process in Harris and Harris, Digital Design and Computer Architecture (2nd ed.), Table 7.6: clock-to-Q 30 ps, memory read 250 ps, register file read 150 ps, multiplexer 25 ps, ALU 200 ps, register file setup 20 ps. As in their analysis, the control unit's delay is assumed to be off the critical path. The rule period ≥ clock-to-Q + logic + setup is the one from the Clocks and timing lesson.