Inside one cell
SRAM means static random-access memory. It stores each bit in a cell of six transistors. The large drawing is one cell, blown up. The grid beside it is a small memory made of many cells; the ringed one is the cell drawn large.
An inverter outputs the opposite of its input. Two inverters feed each other in a loop. Q = 1 makes Q̄ (Q bar) 0, and Q̄ = 0 keeps Q at 1. The loop holds itself steady, like a latch. Each inverter has two transistors.
The other two transistors, the access transistors, are doors between the cell and the outside. Their gates join one wire, the word line. Word line 0: the doors are shut and the cell is cut off. Word line 1: both doors open.
Through the doors the cell reaches two bit lines: BL on the Q side and BL̄ on the Q̄ side. Every cell in a column shares this pair. At the bottom, the read and write circuit watches or drives the two lines.
Read, write, hold
To read, both bit lines are first charged to 1. Then the word line opens the doors. The side holding 0, here Q̄, pulls its bit line down a little. The sense amplifier spots which line dropped and reports Q = 1.
To write 0, the write driver forces BL to 0 and BL̄ to 1, then the word line opens the doors. The strong driver overpowers the small inverters, the loop flips, and the cell now holds Q = 0.
With the word line back at 0, the loop keeps its bit for as long as the power stays on. Nothing has to top it up, so it is called static. Switch the power off, though, and the bit is lost.
The memory array
A memory puts its cells in rows and columns. All the cells in one row share a word line. All the cells in one column share a pair of bit lines. This small array has 4 rows of 4 bits.
A row decoder reads the row address, here 2 bits, and raises exactly one of the 4 word lines. Address 10, which is 2 in binary, opens row 2, and all 4 of its cells reach their bit lines at once.
Six transistors per bit make SRAM fast but large. DRAM needs only one transistor and one capacitor per bit. So SRAM is used where speed matters most: the CPU's registers and caches. Main memory is DRAM.
Tables and code
;; step 1/10 · one-bit ;; about: Cross-coupled inverters, Access transistors, Memory array one SRAM cell = one bit 2 inverters 4 transistors 2 access doors 2 transistors --------------------------- total 6 transistors random access: any cell can be reached directly, in any order
A 6T SRAM cell is two cross-coupled CMOS inverters (two transistors each) plus two access transistors whose gates are the word line (Weste and Harris, CMOS VLSI Design, section 12.2). On a read both bit lines are precharged high; the side of the cell that holds 0 slowly discharges its bit line, and a sense amplifier detects the small difference. On a write the driver is strong enough to overpower the cell's weak pull-up transistors.