Timing closure: making every path fast enough
After synthesis and placement, every path from one flip-flop to the next must deliver its value before the next clock tick. Work through a real sum in nanoseconds: add up the delays to get the arrival time, subtract the setup time from the clock period to get the required time, and read the slack. Then fix a failing path five ways, and meet the hold check, the one a slower clock can never fix.
5 quick questions
Pick an answer to see why. Your score saves with your progress.
01A path's value arrives 3.2 ns after the clock tick. The clock period is 4.0 ns and the setup time is 0.3 ns. What is the slack?
Required time = period − setup = 4.0 − 0.3 = 3.7 ns. Slack = required − arrival = 3.7 − 3.2 = +0.5 ns. Positive: the path meets timing with half a nanosecond to spare.
02What does static timing analysis do?
Static timing analysis works from the cell and wire delays alone. It needs no test inputs, so it covers every path, and it reports the slack of each one; the worst negative slack (WNS) shows whether timing is closed.
03A path has −0.9 ns of slack. Which change does NOT help it?
A higher frequency means a shorter period, so the value is required even earlier and the slack gets worse. The other three shorten the path (or split it) and add slack.
04Pipelining split a 5.5 ns path into two stages of 2.5 ns and 3.5 ns. What is the cost?
The two stages add up to 6.0 ns, not 5.5 ns, because the new flip-flop adds its own 0.5 ns clock-to-Q at the start of stage 2. It holds the half-finished value for one tick, so each result arrives one tick later (more latency). A new value can still start every tick, so throughput stays the same.
05A short path has a hold slack of −0.1 ns. Why will slowing the clock not fix it?
The hold check is tccq + tcd ≥ thold: the new value must not arrive before the hold time after the same edge. No clock period appears, so the fix is to add delay, such as buffers, to the short path.
Glossary
- Timing path
- The route a value takes from one flip-flop's output, through gates and wires, to the next flip-flop's input.
- Arrival time
- When the new value reaches the end of a path: the sum of the clock-to-Q delay and every gate and wire delay on the way.
- Required time
- The latest the value may arrive and still be captured: for setup, the clock period minus the setup time.
- Slack
- Required time minus arrival time. Zero or more means the path meets timing; negative means it fails.
- Static timing analysis (STA)
- A tool that computes the slack of every path from the cell and wire delays, without test inputs.
- Setup time
- How long before a clock edge a flip-flop's input must already be steady.
- Hold time
- How long after a clock edge a flip-flop's input must stay steady, so a new value must not arrive too early.
- Timing closure
- The work of changing a design until every path has zero or positive slack, for both setup and hold.
Notes and sources
- Setup check for a path between two flip-flops: Tc ≥ tpcq + tpd + tsetup. Slack is how much room is left: required time (Tc − tsetup) minus arrival time (tpcq + tpd). Harris and Harris, Digital Design and Computer Architecture, section 3.5.
- Hold check: tccq + tcd ≥ thold, using the fastest delays. The clock period is not in it, so slowing the clock never fixes a hold violation; adding buffers to the short path does (Harris and Harris, section 3.5.2).
- Static timing analysis computes arrival and required times for every path from the cell and wire delays, with no test inputs, and reports the slack of each (Bhasker and Chadha, Static Timing Analysis for Nanometer Designs). AMD Vivado's timing summary reports the worst negative slack (WNS) for setup and the worst hold slack (WHS); the design meets timing when both are zero or more (UG906).
- Common fixes for negative setup slack: restructure the logic, pipeline the path, use faster (upsized) cells, place parts closer to shorten routes, or relax the clock (AMD UG949, UltraFast Design Methodology Guide; Weste and Harris, CMOS VLSI Design, chapter 4).
- The delays here (0.5 ns clock-to-Q, 1.0 ns per gate, 1.0 ns long wire, 0.4 ns setup, 0.5 ns hold) are round example numbers on the nanosecond scale of an FPGA design. Real tools read each cell's delays from the chip's timing library and also add clock skew and uncertainty, which this example leaves at zero. The example hold time (0.5 ns) is set above the fastest clock-to-Q (0.3 ns) so the short path fails; real flip-flops are usually built with clock-to-Q longer than the hold time, so two flip-flops joined by a bare wire normally pass hold, and real hold failures mostly come from clock skew (Harris and Harris, sections 3.5.2 and 3.5.3).
- In Python, 200e6 is 200 × 10⁶ (200 MHz), so 1 / 200e6 is the period in seconds and × 1e9 turns it into nanoseconds.
- Harris and Harris, Digital Design and Computer Architecture (section 3.5: setup and hold; 3.6: pipelining)
- Bhasker and Chadha, Static Timing Analysis for Nanometer Designs (Springer)
- AMD UG906: Vivado Design Analysis and Closure Techniques (WNS, WHS, timing summary)
- AMD UG949: UltraFast Design Methodology Guide (timing closure)
- Weste and Harris, CMOS VLSI Design, 4th ed. (delay and transistor sizing)
- MIT OpenCourseWare 6.004 Computation Structures (sequential logic timing)
- Python docs: binary bitwise operations
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