TLB10 → F1 rw21 → F3 rw32 → diskpage 0A0page 1A1page 2A2MMUframe 0B0frame 1A0frame 2B1frame 3A1frame 4free10 → F0 r-21 → F2 rw32 → diskpage 0B0page 1B1page 2B2A2 · B2✓ TLB hit✗ TLB miss✗ page fault✗ read only
Rows of blocks: pages of 4 KiB (programs A and B) and frames of RAM, each the same sizeWhite token: a virtual address; slate token: the physical address it becomesCards: the page tables, one line per page (frame and protection bits)TLB: a tiny cache of translations next to the MMUTwo programs each see their own addresses; the MMU translates every virtual address through that program's page table to a frame of RAM, keeping the 12-bit offset. The TLB saves recent translations so most accesses skip the table. A page that is not in RAM causes a page fault, and the operating system loads it from disk. Page-table entries carry permission bits; on x86-64 they include read/write, user/supervisor and execute-disable. An access that breaks them raises a page-fault exception, and on Linux the program is usually stopped with a segmentation fault (Intel SDM, volume 3A, sections 4.6 and 4.7).

Address spaces

  1. Two programs, A and B, are running. Each one sees its own private memory, numbered from address 0 upward. This is its virtual address space: the addresses are names the program uses, not real places in RAM.

Translation

Faults and protection

Numbers and code

;; step 1/10 · own-space
;; about: Program A, Program B
virtual address: the address a program
uses in its own code
physical address: a real place in RAM

A reads 0x1234   (its own 0x1234)
B reads 0x1234   (its own 0x1234)

0x means hexadecimal (base 16):
0x1234 = 4,660

Each process has its own virtual address space and its own page table; memory is managed in fixed-size pages (virtual) and frames (physical), and the page offset is copied unchanged while the page number is translated (Patterson and Hennessy, Computer Organization and Design, section 5.7; Arpaci-Dusseau, Operating Systems: Three Easy Pieces, chapter 18). A TLB is a small cache of recent translations. Typical values: 16 to 512 entries, a hit in 0.5 to 1 clock cycle, a miss costing 10 to 100 cycles, and a miss rate of 0.01% to 1% (Patterson and Hennessy, section 5.7).