From design to silicon: the ASIC flow
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Follow one chip from a few lines of Verilog to a packaged part. Synthesis turns the code into standard cells, physical design places them, grows a clock tree and routes metal wires, sign-off checks timing, DRC and LVS, and tape-out sends the layout to the factory. There, light prints it onto a wafer layer by layer over months, and every die is tested and packaged. Finish with what a process node name really measures and why masks cost millions.
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01What does synthesis produce from RTL code?
Synthesis maps the RTL onto ready-made cells from a standard-cell library, such as sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__dfxtp_1, and lists how they connect. Placement and routing come later.
02Why does a chip need a clock tree instead of one long clock wire?
With one long wire, the far flip-flops would see each clock edge later than the near ones. A balanced tree of wires and buffers gives each flip-flop a path of about the same length, so the skew stays small.
03A chip runs at 1 GHz. A path between two flip-flops has a total delay (including setup time) of 0.82 ns. What is the slack?
At 1 GHz one clock period is 1 ns. Slack = 1.00 − 0.82 = +0.18 ns. Positive slack means the signal arrives in time; negative slack would be a timing failure.
04What does LVS (layout versus schematic) check?
LVS rebuilds the circuit from the shapes in the layout and compares it with the netlist. Width and spacing rules are DRC (design rule check); speed is timing sign-off.
05On chips sold as "5 nm", how large is the contacted gate pitch according to the IRDS roadmap?
IEEE Spectrum (2020), quoting the IRDS roadmap, gives about 48 nm for the gate pitch and 36 nm for the metal pitch of 5 nm chips. The node name is a generation label, not a measured size. 13.5 nm is the wavelength of EUV light.
المسرد
- ASIC
- Application-specific integrated circuit: a chip designed for one job and made in a factory, unlike an FPGA, which is rewired after it is made.
- RTL
- Register-transfer level: code, in a hardware language such as Verilog, that describes what each register stores on every clock tick.
- Netlist
- The output of synthesis: a list of standard cells and the wires (nets) that join them.
- Standard cell
- A ready-made gate or flip-flop from the factory's library, drawn to one fixed height so cells line up in rows.
- Clock skew
- The difference in arrival time of the same clock edge at different flip-flops. A clock tree keeps it small.
- Slack
- How much time a signal has to spare: the clock period minus the path delay. Negative slack means a timing failure.
- DRC and LVS
- Design rule check (every shape obeys the factory's width and spacing rules) and layout versus schematic (the layout is the same circuit as the netlist).
- Tape-out
- The moment the finished layout is sent to the factory, usually as a GDSII file, so the masks can be made.
الملاحظات والمصادر
- The steps follow the standard ASIC flow described in Weste and Harris, CMOS VLSI Design (4th ed.), and used by the open OpenROAD tools: synthesis, floorplan, placement, clock tree synthesis, routing, sign-off, then tape-out.
- Cell names are from the open SkyWater SKY130 high-density library (sky130_fd_sc_hd__and2_1, a 2-input AND, and sky130_fd_sc_hd__dfxtp_1, a flip-flop). SKY130 has one local-interconnect layer and five metal layers.
- The delays in the timing step are example numbers chosen to show the sum, not values from a real cell library. At 1 GHz one clock period is 1/1,000,000,000 s = 1 ns.
- Bloomberg Businessweek (2016) reported that Intel's wafers take about three months and more than 2,000 steps of lithography, etching and deposition. ASML's EUV machines print with 13.5 nm light; leading fabs such as TSMC's process 300 mm (12-inch) wafers.
- IEEE Spectrum (2020): the critical features of a 7 nm transistor are much larger than 7 nm, and the IRDS roadmap puts 5 nm chips at a 48 nm contacted gate pitch and a 36 nm metal pitch.
- EE Times (2008) put a leading-edge 45 nm mask set at $2 million to $2.2 million and a 32 nm set at about $4 million; sets for newer nodes cost more.
- Weste and Harris: CMOS VLSI Design, 4th edition (Harvey Mudd)
- OpenROAD documentation: the open RTL-to-GDSII flow
- IEEE Std 1364-2005: Verilog Hardware Description Language
- SkyWater SKY130 PDK: sky130_fd_sc_hd and2 cell
- SkyWater SKY130 PDK: sky130_fd_sc_hd dfxtp cell
- SkyWater SKY130 PDK: process layers and assumptions
- Bloomberg Businessweek: How Intel Makes a Chip (2016)
- ASML: EUV lithography systems
- TSMC: GIGAFAB facilities (300 mm wafers)
- IEEE Spectrum: A Better Way to Measure Progress in Semiconductors (2020)
- EE Times: Toppan rolls 32-nm masks, but can industry afford it? (2008)
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