Lesson 19 · Memory elements and clocks

The D flip-flop

A gated D latch copies its data input D to its output Q while enable is 1 and holds Q while enable is 0. That makes it react for as long as enable stays high. Join two latches on opposite clocks and you get an edge-triggered D flip-flop: it captures D only at the clock's rising edge and holds it for the whole cycle, as long as D is steady for a short setup and hold time around that edge.

12 min10 steps5 questionsIntermediate

Fig 19 · Interactive

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5 quick questions

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01A gated D latch has enable = 1. D changes from 0 to 1. What does Q do?

While enable is 1 the latch is transparent, so Q follows D straight away.

02What is the rising edge of a clock?

The rising edge is the instant the clock jumps from 0 up to 1. An edge-triggered flip-flop captures D then.

03In a leader-follower D flip-flop, which latch is open while the clock is 0?

A NOT gate gives the leader the flipped clock, so it is open while the clock is 0. The follower is open only while the clock is 1, so they are never open together.

04D flickers several times while the clock is 1. What happens to a D flip-flop's Q?

During the 1 part of the clock the leader is closed, so changes on D cannot reach Q. Q keeps the bit captured at the rising edge until the next one.

05The SN74LVC74A at 3.3 V needs a setup time of 3 ns and a hold time of 1 ns. What does that mean?

Setup time is how long D must be steady before the edge; hold time is how long it must stay steady after it.

Key terms

Glossary

Gated D latch: A one-bit memory with a data input D and an enable E. While E is 1, Q copies D; while E is 0, Q holds its value.
Transparent: Said of a latch whose enable is on: the output follows the input, as if looking through a window.
Level-sensitive: Reacting for the whole time a signal is at a level (for example, while enable is 1), not at one instant.
Clock: A signal that switches between 0 and 1 at a steady rate, so that many parts of a circuit can act in step.
Rising edge: The instant a clock (or any signal) goes from 0 to 1.
Edge-triggered D flip-flop: Two D latches in a row on opposite clocks. Q copies D only at the clock's rising edge and holds it for the rest of the cycle.
Setup time: How long D must be steady before the clock edge for the flip-flop to capture it correctly.
Hold time: How long D must stay steady after the clock edge.

Fine print

Notes and sources

A gated D latch is transparent (Q follows D) while its enable is 1 and holds Q while it is 0. Because it reacts for the whole time enable is 1, it is called level-sensitive (Harris and Harris, Digital Design and Computer Architecture, section 3.2).
An edge-triggered D flip-flop is two D latches in a row on opposite clocks. Textbooks call them master and slave; here they are the leader and the follower. Q copies D only at the rising edge of the clock and holds it for the rest of the cycle.
Texas Instruments' SN74LVC74A holds two positive-edge-triggered D flip-flops. At 3.3 V its datasheet requires D to be steady at least 3 ns before the clock's rising edge (setup time) and 1 ns after it (hold time), with a clock of up to 100 MHz.
In the figure each column of the timing card is one moment. Real clocks tick far faster; the frames are slowed down so you can watch them.

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