Lesson 25 · Memory

DRAM: memory made of leaky buckets

Dynamic RAM stores each bit as charge on a tiny capacitor behind a single transistor. That makes it far denser and cheaper than SRAM, but the charge leaks. Watch one cell write a 1 and a 0, see a grid of cells drain, open a row, sense it, write it back, pick a column, and keep every row alive with refresh. Then see why main memory is DRAM.

12 min11 steps5 questionsBeginner

Fig 25 · Interactive

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5 quick questions

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01What does a DRAM cell use to store one bit?

The bit is charge on a capacitor (full = 1, empty = 0), and one access transistor connects it to the bit line when the word line turns it on. Six transistors is SRAM.

02Why does DRAM need refresh?

The charge leaks away. Refresh opens each row and lets the sense amplifiers write it back at full strength, in time for every row.

03Under the DDR4 standard at normal temperatures, every row must be refreshed at least once every:

64 ms (32 ms above 85 °C). The chip spreads this over 8192 refresh commands, one about every 7.8 µs.

04Why is reading a DRAM row called destructive?

A cell holds much less charge than its bit line, so after sharing, the cell sits near half. The sense amplifiers drive the full 0 or 1 back to restore it.

05Why is a computer's main memory made of DRAM and not SRAM?

One transistor and one capacitor per bit makes DRAM dense and cheap. SRAM is faster and needs no refresh, but six transistors per bit make it bulky, so it is used for caches.

Key terms

Glossary

DRAM: Dynamic random-access memory: memory that stores each bit as charge on a capacitor and must be refreshed because the charge leaks.
Capacitor: A tiny store of electric charge. In a DRAM cell, full stands for 1 and empty for 0.
1T1C cell: One transistor plus one capacitor: the DRAM cell. The transistor is the door between the capacitor and the bit line.
Word line / bit line: A word line runs along a row and opens the doors of all its cells; a bit line runs along a column and carries charge in and out of its cells.
Sense amplifier: A circuit at the end of each bit line that turns a tiny voltage nudge into a clear 0 or 1 and writes it back. Together they form the row buffer.
Refresh: Reading and rewriting every row on a schedule so leaking charge never fades too far. DDR4 requires every row within 64 ms at normal temperatures.
Bank: An independent grid of cells inside a DRAM chip, with its own rows and sense amplifiers. DDR4 chips have 8 or 16.
SRAM: Static RAM: six transistors per bit, fast and needs no refresh, but bulky. Used for caches.

Fine print

Notes and sources

The one-transistor, one-capacitor cell was invented by Robert Dennard at IBM (US patent 3,387,286, granted in 1968). Almost every DRAM chip since stores bits this way.
The figure runs enormously slowed down. Real DRAM cells keep their charge for tens of milliseconds or longer, and the standard refreshes each row at least every 64 ms.
A cell holds far less charge than its long bit line, so sharing moves the bit line only slightly. That is why a sense amplifier is needed, and why the cell is left near half full until it is written back (Harris and Harris, section 5.5; Drepper, section 2.1).
Micron's 8 Gb DDR4 datasheet (following JEDEC JESD79-4): 8192 refresh commands every 64 ms at 0 to 85 °C, one about every 7.8 µs on average; 32 ms above 85 °C.
DDR4 chips with 4- or 8-bit data paths have 16 banks in 4 bank groups; 16-bit chips have 8 banks in 2 groups. An 8 Gb x8 chip has 65,536 rows and 1,024 columns per bank. Banks can have rows open at the same time, but a DDR4 REFRESH command covers all banks at once: every bank must first close its row. Refreshing one bank while others work exists only in newer chips (LPDDR, and DDR5's same-bank refresh).
An SRAM cell is two inverters feeding each other plus two access transistors: six transistors that hold the bit as long as power is on, with no refresh.

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