FPGAs
An FPGA is a chip you can rewire after it is made. Its fabric is a grid of logic tiles, each a lookup table (LUT) beside a flip-flop, joined by routing switches, with blocks of RAM and DSP maths among them. Watch a 4-input LUT become AND and then XOR just by changing its 16 stored bits, see a flip-flop hold a value, light a path through the routing, and load a bitstream that configures it all.
5 quick questions
Pick an answer to see why. Your score saves with your progress.
01What does the one configuration bit inside a routing switch decide?
Each switch sits where tracks cross. Its bit closes it (1) to link the tracks or leaves it open (0), so the bitstream decides which tiles are wired together.
02A 4-input LUT should act as a 4-input AND gate. What must its 16 cells hold?
AND gives 1 only when all inputs are 1, so only the last cell (picked by 1 1 1 1) stores a 1.
03What does the flip-flop next to a LUT do?
On each rising clock edge the flip-flop copies its input and keeps it, even if the LUT's output changes in between. That gives the circuit memory.
04Why does an SRAM-based FPGA load its bitstream again every time it powers up?
SRAM is volatile. The bitstream usually waits in a flash chip on the board and is copied into the FPGA at every start.
05Which job suits an FPGA better than a custom-made chip?
An FPGA can be reprogrammed as often as you like, so it fits prototypes, small batches and accelerators. For huge volumes a custom chip is cheaper per unit.
Glossary
- FPGA
- Field-programmable gate array: a chip of configurable logic blocks and wiring that you set up after it is made.
- Lookup table (LUT)
- A small memory whose inputs pick one stored bit; with the right bits it can be any logic function of its inputs.
- Flip-flop
- A one-bit memory that copies its input when the clock ticks and holds it until the next tick.
- Routing
- The wire tracks between tiles, joined by programmable switches that each hold one configuration bit.
- Block RAM
- A fixed memory block built into the FPGA fabric; on AMD 7 series chips each holds 36 Kb.
- DSP slice
- A fixed block for fast arithmetic such as multiply and add (DSP: digital signal processing).
- Bitstream
- The file that holds every configuration bit for one design; loading it sets up the FPGA.
- Configuration memory
- The memory cells inside the FPGA that hold the loaded bitstream; on most FPGAs it is SRAM.
Notes and sources
- A k-input LUT is 2 to the power k one-bit memory cells plus a selector: the inputs choose which cell's bit reaches the output. The 4-input LUT here is the one in each logic element of an Intel Cyclone IV (Harris and Harris, Digital Design and Computer Architecture, section 5.6.2).
- Newer FPGAs use bigger LUTs: each slice of an AMD (Xilinx) 7 series chip has four 6-input LUTs and eight flip-flops (UG474).
- Block RAM and DSP figures are for AMD 7 series: 36 Kb per block RAM (UG473) and a 25 × 18 bit multiplier with a 48-bit accumulator per DSP48E1 slice (UG479).
- 7 series configuration memory is volatile SRAM, so the bitstream is loaded again after every power-up, usually from a flash chip on the board (UG470). Some FPGA families store their configuration in flash instead and keep it with the power off.
- In Python a list can stand in for the LUT: lut[i] reads cell i, and a << 3 | b << 2 | c << 1 | d turns four 0/1 inputs into a cell number from 0 to 15.
- Harris and Harris, Digital Design and Computer Architecture (section 5.6.2: FPGAs)
- AMD UG474: 7 Series FPGAs Configurable Logic Block User Guide
- AMD UG473: 7 Series FPGAs Memory Resources (block RAM)
- AMD UG479: 7 Series DSP48E1 Slice User Guide
- AMD UG470: 7 Series FPGAs Configuration User Guide
- Intel Cyclone IV Device Handbook (logic elements with 4-input LUTs)
- Kuon, Tessier and Rose, FPGA Architecture: Survey and Challenges (2008)
- Python tutorial: lists
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