Lesson 18 · Memory elements and clocks

The SR latch

Gates on their own forget: their output depends only on their inputs right now. Wire two NOR gates in a loop, so each output feeds the other gate, and the circuit can remember one bit. Step through set, hold, reset and hold, watch the feedback loop keep the value, see why S = R = 1 is not allowed, and meet the NAND version with active-low inputs.

12 min9 steps5 questionsIntermediate

Fig 18 · Interactive

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5 quick questions

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01In a NOR SR latch, Q is 1. Then S = 0 and R = 0. What is Q?

S = R = 0 is the hold case: Q feeds a 1 into gate 2, which keeps Q̄ at 0, which keeps Q at 1. The latch remembers.

02What does the input R = 1 (with S = 0) do to a NOR SR latch?

R is the reset input. Gate 1 gets a 1, so Q goes to 0; then gate 2 sees 0 and 0 and Q̄ goes to 1.

03Why is S = 1 and R = 1 not allowed in a NOR SR latch?

Both gates get a 1, so both outputs are 0 and are no longer opposites. If S and R drop together, the gates race: either state can win, and in an ideal model the loop may even oscillate for a while.

04What makes the SR latch able to remember, when a single gate cannot?

The loop lets the outputs hold each other steady, so the output depends on what happened before, not just on the inputs now.

05In the NAND version of the latch, how do you set Q to 1?

The NAND latch has active-low inputs: they rest at 1 and act at 0. A 0 on S̄ sets Q to 1; both at 1 holds.

Key terms

Glossary

Latch: A small circuit that stores one bit and keeps it until it is told to change.
Feedback: Wiring an output back into an input of the same circuit, so the circuit's past affects its present.
Cross-coupled: Two gates wired so that each one's output feeds an input of the other.
Set and reset: Set makes the stored bit Q equal 1; reset makes it 0.
Q and Q̄: The latch's two outputs. Q is the stored bit; Q̄ (Q-bar) is its opposite.
Hold: Leaving both inputs inactive, so the latch keeps its last value.
Active-low: An input that does its job when it is 0 rather than 1, marked with a bar over its name (S̄, R̄).
Sequential circuit: A circuit whose output depends on past inputs as well as present ones, because it stores state.

Fine print

Notes and sources

A circuit whose output depends only on its inputs right now is called combinational (gates, adders, the ALU). Feedback makes a circuit sequential: its output also depends on what happened before (Harris and Harris, Digital Design and Computer Architecture, section 3.2).
The rules of the NOR SR latch: S = 1 sets Q = 1, R = 1 resets Q = 0, S = R = 0 holds, S = R = 1 forces Q = Q̄ = 0 and is not allowed (Harris and Harris, section 3.2, Latches and Flip-Flops).
If S and R fall from 1 to 0 at the same moment, both gates try to switch to 1 and the final state depends on tiny timing differences: a race. Designs avoid it by never asserting S and R together.
In the figure the gates change one after another so you can follow the loop. In a real chip each gate takes a tiny delay (nanoseconds or less), so the whole loop settles almost at once.
The NAND form has active-low inputs S̄ and R̄ (rest at 1, act at 0). Texas Instruments puts four in one chip: the SN74LS279A, "quadruple S̄-R̄ latches" (two of the four have two S̄ inputs).
In Python, | on the numbers 0 and 1 is OR, so NOR of two bits is 1 - (a | b). The loop runs a few times so the two gates can settle.

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