Lesson 24 · Memory

SRAM

Static RAM keeps each bit in a cell of six transistors: two inverters joined in a loop hold the bit, and two access transistors, opened by a word line, connect it to a pair of bit lines. Watch one cell blown up as it holds, is read and is written, then see a small grid of cells where a row decoder opens one row at a time. Find out why SRAM is fast, needs no refresh, and is still too big to use for all of a computer's memory.

12 min10 steps5 questionsIntermediate

Fig 24 · Interactive

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5 quick questions

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01How many transistors does one standard SRAM cell use to store one bit?

Four transistors make the two inverters that hold the bit, and two more are the access transistors: six in all.

02What does the word line do?

The word line drives the gates of the access transistors. At 1 the doors open and the cells in that row reach their bit lines; at 0 they are cut off.

03During a read, both bit lines start at 1. The cell holds Q = 1. What happens when the word line opens the doors?

The side holding 0 pulls its bit line down. Here that is Q̄, so BL̄ dips and the sense amplifier reads a 1. The cell keeps its bit.

04A memory array has 4 rows. How many address bits does its row decoder need, and how many word lines does it raise at a time?

n address bits name 2^n rows, so 2 bits cover 4 rows. The decoder raises exactly one word line: the row the address names.

05Why is SRAM used for caches but not for all of a computer's main memory?

SRAM is fast and needs no refresh, but six transistors per bit make it large and costly. DRAM packs a bit into one transistor and one capacitor, so main memory uses DRAM.

Key terms

Glossary

SRAM (static RAM): Memory that keeps each bit in a loop of two inverters. It holds the bit while powered and needs no refresh.
Inverter: A gate whose output is the opposite of its input. A CMOS inverter uses two transistors.
Cross-coupled inverters: Two inverters each feeding the other's input. The loop holds itself in one of two steady states: a stored bit.
Access transistor: One of the two transistors that act as doors between an SRAM cell's storage nodes and its bit lines.
Word line: The wire along a row that opens the access transistors of every cell in that row.
Bit lines: A pair of wires, BL and BL̄, down a column. Data is read from and written to the cells through them.
Sense amplifier: A circuit that detects which of two bit lines has dropped a little and turns that into a clean 0 or 1.
Row decoder: A circuit that turns an n-bit row address into exactly one raised word line out of 2^n.

Fine print

Notes and sources

A 6T SRAM cell is two cross-coupled CMOS inverters (two transistors each) plus two access transistors whose gates are the word line (Weste and Harris, CMOS VLSI Design, section 12.2).
On a read both bit lines are precharged high; the side of the cell that holds 0 slowly discharges its bit line, and a sense amplifier detects the small difference. On a write the driver is strong enough to overpower the cell's weak pull-up transistors.
In an array every cell of a row shares a word line and every cell of a column shares a bit line pair; a decoder turns an n-bit row address into exactly one of 2^n word lines (Harris and Harris, Digital Design and Computer Architecture, section 5.5).
A DRAM cell is one transistor and one capacitor. The charge leaks, so DDR4 DRAM refreshes every row within 64 ms (JEDEC JESD79-4). SRAM needs no refresh but uses six transistors per bit, so it is used for caches and register files (Hennessy and Patterson, section 2.2).
Both SRAM and DRAM are volatile: they lose their data when the power is switched off. Flash memory is the kind that keeps it.

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